The present invention relates to a semiconductor device and an automobile control system having the same, and particularly to a technology for reducing power consumption.
Patent document 1 (Japanese Patent Laid-Open No. 2006-287736) describes a detection circuit and a semiconductor device which can efficiently detect stop of an external clock with a simple circuit configuration. The semiconductor device has a PLL circuit which generates a PLL (Phase-Locked Loop) output clock by multiplying an oscillation clock, an internal circuit which operates based on the PLL output clock, and an oscillation stop detection circuit which detects, based on the oscillation clock and the PLL output clock, stop of the oscillation clock, and outputs the detected result to the internal circuit.
Patent document 2 (Japanese Patent Laid-Open No. 2003-177834) describes a technology for configuring a stop detection unit of an external oscillator circuit with a simple structure and a small circuit footprint. In a microcomputer having a built-in PLL circuit according to the patent document 2, when an output of a counter, which is cleared by an output of an edge detection circuit for detecting an edge of an externally-generated clock signal that is input and which performs a count operation using an internal clock signal output from the PLL circuit as a count source, exceeds a predetermined setting value, it is detected as stop of the externally-generated clock signal and an external clock stop detection signal is output.
Patent document 3 (Japanese Patent No. 4216282) describes a semiconductor integrated circuit device which can reliably prevent malfunction or the like even if any abnormality such as stop of an externally coupled clock oscillator has occurred. According to the patent document 3, the circuit has a clock generating unit which detects the signal state of an oscillation signal generated by an external oscillator externally coupled to an oscillation signal terminal, and generates a clock signal based on an oscillation signal of the external oscillator if the oscillation signal of the external oscillator is normal, or generates a system clock signal based on an internal oscillation signal if the oscillation signal of the external oscillator is abnormal.
Patent document 4 (Japanese Patent Laid-Open No. 2006-127466) describes a microcomputer which stops the oscillator circuit and the PLL circuit upon transiting to a low power consumption mode and starts processing of the CPU faster when the low power consumption mode is canceled. According to the patent document 4, the oscillation condition that has been set at the time of transiting to the low power consumption mode is held, and when the oscillation is resumed, the oscillator circuit is operated based on the held oscillation condition.